• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A method of forming a silicide blocking layer is disclosed. A silicide blocking layer is formed on a semiconductor substrate by a plasma-enhanced chemical vapor deposition (PE-CVD) method. The silicide blocking layer in the region where the metal silicide contact is to be formed is removed by a wet etching method. After the metal layer is formed on the resultant, silicidation reaction between the silicon in the region and the metal of the metal layer forms metal silicide. Since the silicide blocking layer made of PE-SiON is formed at a low temperature of 400 ° C. or lower, it is possible to suppress diffusion and redistribution of impurities in the gate and source / drain regions of the transistor during deposition of the silicide blocking layer.
    公开号:KR20020085978A
    申请号:KR1020010025552
    申请日:2001-05-10
    公开日:2002-11-18
    发明作者:박정훈
    申请人:삼성전자 주식회사；
    IPC主号:
    专利说明:

    Method of forming silicidation blocking layer
    [10] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of selectively silicidating a predetermined region on a semiconductor substrate.
    [11] As semiconductor devices are highly integrated, not only the size of the pattern formed on the chip is smaller, but also the gap between the patterns is becoming narrower. In the past, polysilicon was a very useful material for wiring materials such as gate electrodes and bit lines, but as the patterns became smaller, polysilicon's resistivity became too large, resulting in an increase in RC time delay and IR voltage drop. In addition, the source / drain region is formed at the same time as the junction depth of the source / drain region is shallow to improve the short channel effect and the punchthrough due to the decrease in the gate length of the transistor. Parasitic resistances such as sheet resistance and contact resistance should be reduced.
    [12] As a result, a new metallization process is a self-aligned silicide (silicide) that can form silicides on the surfaces of the gate and source / drain regions, thereby reducing the resistivity of the gate and the parasitic resistance of the source / drain regions. It is used as a process. The salicide process is a process of selectively forming silicide only in the gate electrode and the source / drain regions. Such silicide is formed of a material such as titanium silicide (TiSi 2 ) or group VIII silicide (PtSi 2 , PdSi 2 , CoSi 2 , and NiSi 2 ), and in a semiconductor device having a design rule of 0.25 μm, the gate critical dimension Cobalt silicides with less dependence on critical dimension (CD) are mainly used. Cobalt silicide is known to have a low specific resistance of 16 to 18 mu OMEGA -cm and to have stable properties even at a high temperature of about 900 ° C.
    [13] On the other hand, in the case of the logic element using the cobalt silicide as the gate electrode material, the formation of the silicide should be excluded because the gate is used as the resistive component in the analog region. Accordingly, in order to selectively form silicide only in a desired region, a silicidation blocking layer (SBL) made of a material that does not react with the metal layer must be formed before deposition of the silicide metal layer.
    [14] 1A to 1C are cross-sectional views illustrating a method of manufacturing a logic device having a silicide blocking layer by a conventional method.
    [15] Referring to FIG. 1A, a field oxide layer 11 is formed on a silicon substrate 10 by a conventional shallow trench isolation process to define an active region 12 in the substrate 10. . Subsequently, after forming the gate oxide film 14 on the active region 12 of the substrate 10, a polysilicon layer is deposited thereon. After the polysilicon layer is doped to a high concentration of N-type by a conventional doping method such as POCl 3 diffusion, ion implantation, or in-situ doping, the polysilicon layer is patterned by a photolithography process to form an N + gate electrode ( 16).
    [16] An insulating material such as silicon oxide or silicon nitride is deposited on the gate electrode 16 and the substrate 10 by chemical vapor deposition (CVD), and then anisotropically etched to form the gate electrode 16. The gate spacers 18 are formed on the sidewalls of the gate spacers 18. Subsequently, a source / drain region (not shown) is formed on the surface of the substrate on both sides of the gate electrode 16 through an ion implantation process. As a result of the above-described process, a MOS transistor consisting of the gate electrode 16 and the source / drain regions is completed.
    [17] Next, an oxide is deposited on the MOS transistor and the substrate 10 by a chemical vapor deposition (CVD) method at a temperature of about 750 ° C. to form a buffer layer 20. Silicon nitride is deposited on the buffer layer 20 at a temperature of about 670 ° C. by low pressure chemical vapor deposition (LPCVD) to a thickness of about 100 to 200 kPa. To form. The buffer layer 20 serves to prevent attack of the silicon substrate 10 and the field oxide layer 11 under the silicon oxide layer 10 and the field oxide layer 11 during the subsequent etching process of the silicide blocking layer 22.
    [18] Referring to FIG. 1B, a photoresist pattern 24 is formed on the silicide blocking layer 22 through a photolithography process. The photoresist pattern 24 is formed to open a region where silicide is to be formed. Subsequently, the silicide blocking layer 22 in the region where silicide is to be formed is dry-etched using the photoresist pattern 24 as a mask. Then, a silicide blocking layer pattern (hereinafter referred to as an "SBL pattern") 22a is formed which distinguishes the active region and the inactive region of the silicidation.
    [19] Referring to FIG. 1C, the photoresist pattern 24 is removed by ashing and stripping. The wafer is then placed in a chamber of an RF sputtering facility after performing a conventional wet cleaning process to remove metal impurities, organic contaminants or fine oxides formed on the surfaces of the silicon and polysilicon layers, including fine particles on the wafer.
    [20] Subsequently, RF plasma etching is performed to remove a native oxide film or the like that may be regenerated during the movement of the wafer, and then a cobalt layer is deposited on the wafer in-situ by the sputtering method. Cobalt silicide 26 is formed only in the exposed gate and / or active region by performing two heat treatments using Rapid Thermal Annealing (RTA) or a furnace. At this time, silicide is not formed in the gate and / or the active region covered by the SBL pattern 22a.
    [21] According to the conventional method described above, since the silicide blocking layer is deposited after the gate and source / drain regions are formed, the doped gate and source / drain regions have been doped by a heat budget of 750 ° C / 670 ° C. Impurities diffuse and redistribute. As a result, short-channel effects such as punch-through between the source / drain occur or impurities in the gate electrode penetrate into the channel region through the gate oxide film.
    [22] Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing diffusion of impurities in gate and source / drain regions by depositing a silicide blocking layer at a low temperature.
    [1] 1A to 1C are cross-sectional views illustrating a method of manufacturing a logic device having a silicide blocking layer by a conventional method.
    [2] 2A to 2E are cross-sectional views illustrating a method of manufacturing a logic device having a silicide blocking layer according to the present invention.
    [3] 3 is a graph showing the measurement results of the sheet resistance of the gate electrode according to the present invention.
    [4] <Explanation of symbols for the main parts of the drawings>
    [5] 100 semiconductor substrate 101 field oxide film
    [6] 102 active region 104 gate oxide film
    [7] 106 gate electrode 108 gate spacer
    [8] 110: silicidation stop layer 110a: SBL pattern
    [9] 114: metal layer 116: metal silicide
    [23] In order to achieve the above object, the present invention comprises the steps of forming a silicide blocking layer on a semiconductor substrate by a plasma-enhanced chemical vapor deposition (PE-CVD) method; Removing the silicide blocking layer in the region where a metal silicide contact is to be formed by a wet etching method; Forming a metal layer on the region and the substrate; And silicidating the silicon in the region with the metal of the metal layer to form a metal silicide.
    [24] In addition, the above object of the present invention is to form a transistor having a gate electrode and a source / drain region on the active region of the semiconductor substrate; Forming a silicide stop layer on the transistor and the substrate by a plasma-enhanced chemical vapor deposition (PE-CVD) method; Removing the silicide blocking layer of a portion of the semiconductor substrate by wet etching to form a silicide blocking layer pattern; Forming a metal layer on the silicide stop layer pattern, the transistor, and the substrate; And forming a metal silicide by silicidating a silicon in the partial region of the semiconductor substrate on which the silicide blocking layer pattern is not formed with the metal of the metal layer. It may also be achieved by.
    [25] According to the present invention, silicon oxynitride (SiON) is deposited by a PE-CVD method at a low temperature of about 400 ° C. or less to form a silicide blocking layer. Thus, it is possible to suppress diffusion and redistribution of impurities in the gate and source / drain regions of the transistor during deposition of the silicide stop layer.
    [26] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    [27] 2A to 2E are cross-sectional views illustrating a method of manufacturing a logic device having a silicide blocking layer according to the present invention.
    [28] 2A shows the step of forming MOS transistors TR. First, after preparing a semiconductor substrate 100 such as silicon, a field oxide film 101 is formed on the substrate 100 by a conventional shallow trench isolation process to be active on the substrate 100. Area 102 is defined.
    [29] Subsequently, a gate oxide film 104 made of silicon oxide (SiO 2 ) or silicon oxynitride (SiON) is formed on the surface of the substrate in the active region 102 surrounded by the field oxide film 101 to a thickness of about 60 to 80 占 퐉. do. A polysilicon layer is deposited on the gate oxide film 104 to a thickness of about 2000 to 2500 mW by a low pressure chemical vapor deposition (LPCVD) method. After the polysilicon layer is doped to a high concentration of N-type by a conventional doping method such as POCl 3 diffusion, ion implantation, or in-situ doping, the polysilicon layer is patterned by a photolithography process to form an N + gate electrode ( 106).
    [30] An insulating film is deposited on the entire surface of the substrate 100 to a thickness of about 800 kPa by chemical vapor deposition (CVD). The insulating layer is etched by an anisotropic dry etching method to form a gate spacer 108 on the sidewall of the gate electrode 106. Preferably, the gate spacer 108 is formed of a material, such as nitride or oxide, that can inhibit the silicidation reaction in a subsequent process.
    [31] Subsequently, a high concentration source / drain region (not shown) is formed on the surface of the substrate on both sides of the gate electrode 106 through an ion implantation process. As a result of the above-described process, MOS transistors TR consisting of the gate electrode 106 and the source / drain regions are completed.
    [32] 2B illustrates the step of forming the silicide blocking layer 110. Silicon oxynitite by plasma-enhanced chemical vapor deposition (PE-CVD) method using silane (SiH 4 ) and ammonia (NH 3 ) as a source gas at a temperature of about 400 ° C. or below on the MOS transistor and the substrate 100. The silicide (SiON) is deposited to a thickness of about 300 to 1000 GPa, preferably about 800 GPa to form the silicidation blocking layer 110. In this case, Si 2 H 6 , SiH 2 Cl 2, or SiHCl 3 may be used as the silicon (Si) source gas instead of the SiH 4 . In addition, although silicon nitride (SiN) may be used instead of silicon oxynitride (SiON), it is preferable to use silicon oxynitride (SiON) in terms of etching selectivity to oxide.
    [33] The silicidation blocking layer 110 should be formed to a thickness sufficient to suppress the silicidation reaction while considering the amount consumed in the cleaning process performed before the subsequent deposition of the metal layer.
    [34] In the conventional method, a silicide blocking layer is formed using silicon nitride (SiN) deposited by LPCVD at a high temperature of about 650 to 750 ° C. Thus, impurities in the gate and source / drain regions diffuse and redistribute during deposition of the silicide stop layer, thereby degrading the characteristics of the transistor. In contrast, in the present invention, since the silicide blocking layer is formed using silicon oxynitride (SiON) deposited by PECVD at a low temperature of about 400 ° C. or less, it is possible to suppress diffusion of impurities in the gate and source / drain regions. Can be.
    [35] 2C illustrates forming the SBL pattern 110a. After applying the photoresist film on the silicide blocking layer 110, the photoresist film is exposed and developed to form a photoresist pattern 112 that opens a portion of the silicide-formed region. In this case, the partial region may be a gate region of a transistor or a source / drain region. In addition, the partial region may include both a gate region and a source / drain region of the transistor.
    [36] Subsequently, the exposed silicide blocking layer 110 is removed by using a wet etching method using the photoresist pattern 112 as an etching mask. Then, the silicide blocking layer pattern (SBL pattern) 110a is formed to distinguish between the active region and the inactive region of the silicide.
    [37] The wet etching is performed using an etchant having a silicon oxynitride (SiON) having a high etching selectivity with respect to oxide so as to minimize the consumption of the field oxide film 101. Preferably, the silicide blocking layer 110 is wet-etched using a chemical mixture of hydrofluoric acid (HF), peroxide (H 2 O 2 ), and distilled water (DI water) in a ratio of 1:70:30. . The etching rate of PE-SiON with respect to the chemical is 600-700 kW / min, and the etching rate of oxide is 50 kW / min. That is, when PE-SiON uses an etchant having an etching selectivity of 10: 1 with respect to oxide, the silicide blocking layer 110 may be patterned while minimizing the consumption of the field oxide film 101.
    [38] According to the conventional method, since the silicide blocking layer made of LP-SiN is patterned by a dry etching method, an oxide is deposited on the lower portion of the silicide blocking layer in order to suppress the consumption of the field oxide film and to reduce the etch damage. A buffer layer is formed. In contrast, in the present embodiment, since the silicide blocking layer made of PE-SiON is patterned by a wet etching method, it is not necessary to form a buffer layer under the silicide blocking layer.
    [39] In addition, in the present embodiment, a photoresist pattern is used as a mask for wet etching the silicide blocking layer, but the silicide blocking layer may be wet etched using a hard mask such as a silicon oxide film.
    [40] 2D shows the step of forming the metal layer 114. After forming the SBL pattern 110a as described above, the photoresist pattern 112 is removed by an ashing and stripping process.
    [41] Subsequently, after performing a conventional wet cleaning process for removing contaminants including fine particles on the substrate 100 or a natural oxide film formed on the surface of the silicon region, the substrate 100 is placed in a chamber of an RF sputtering facility. After the RF plasma etching is performed to remove a natural oxide film or the like that may be regenerated during the movement of the substrate 100, a metal layer 114, eg, a cobalt layer, is deposited on the front surface of the substrate by in-situ.
    [42] 2E illustrates forming metal silicide 116. After the substrate 100 is placed in a reaction chamber of a conventional high speed heater, the substrate 100 is first heated at a low temperature of about 400 to 600 ° C. under a nitrogen (N 2 ) atmosphere to contact the metal layer 114 with silicon. Induces a silicide reaction in the region. As a result, metal silicides such as cobalt monosilicide (CoSi) of the first phase are formed on the gate electrode 106 and the source / drain regions of the region where the SBL pattern 110a is not formed, and are covered with the SBL pattern 110a. Silicide is not formed on the region and the gate spacer 108.
    [43] Subsequently, the unreacted metal layer 114 is removed by wet etching using an etchant that does not damage the metal silicide, the substrate 100, and the gate oxide layer 104. Subsequently, after placing the substrate 100 in a reaction chamber of a conventional high speed heater, the substrate 100 is secondarily heated at a high temperature of about 700 to 900 ° C. under a nitrogen (N 2 ) atmosphere. As a result, the metal silicide of the first phase is phase shifted to the metal silicide of the second phase to form a perfect metal silicide 116. For example, when the cobalt layer is formed to a thickness of 100 GPa, a CoSi layer having a thickness of about 200 GPa is formed during the first heat treatment, and a CoSi 2 layer having a thickness of about 400 GPa is formed during the second heat treatment.
    [44] Here, a capping layer made of titanium (Ti) and titanium nitride (TiN) may be formed on the metal layer 114 before the first heat treatment. The capping layer serves to prevent oxidation of the metal and to prevent excessive growth of the metal silicide to an unwanted region.
    [45] 3 is a graph showing the measurement results of the sheet resistance of the gate electrode according to the present invention. Here, the X axis represents the critical dimension (CD) of the gate electrode, and the Y axis represents the sheet resistance of the gate electrode.
    [46] Referring to FIG. 3, PE-SiON is deposited to a thickness of about 800 kPa to form a silicide blocking layer, and then a mixture of hydrofluoric acid (HF), peroxide (H 2 O 2 ), and distilled water (DI water) is used. Wet etching was performed for about 100 seconds to pattern the silicide blocking layer. As a result of measuring the sheet resistance of the N + gate electrode in this state, in the SBL open region A, that is, the region where the SBL pattern is not formed, a constant sheet resistance can be obtained even though the critical dimension of the gate electrode decreases due to the formation of silicide. there was. In addition, in the SBL region B, that is, the region in which the SBL pattern is formed, the sheet resistance of the gate electrode increases as the critical dimension of the gate electrode decreases, indicating that the PE-SiON sufficiently suppressed the silicidation reaction. Able to know.
    [47] As described above, according to the present invention, silicon oxynitride (SiON) is deposited at a low temperature of about 400 ° C. or lower by PE-CVD to form a silicide blocking layer. Thus, the thermal bundle can be reduced to suppress diffusion and redistribution of impurities in the gate and source / drain regions of the transistor during deposition of the silicide stop layer.
    [48] In addition, since the silicide blocking layer is patterned by wet etching, it is possible to minimize the consumption of the field oxide layer without forming the buffer layer. Therefore, the process can be simplified.
    [49] As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.
    权利要求:
    Claims (16)
    [1" claim-type="Currently amended] Forming a silicide blocking layer on a semiconductor substrate by a plasma-enhanced chemical vapor deposition (PE-CVD) method;
    Removing the silicide blocking layer in the region where a metal silicide contact is to be formed by a wet etching method;
    Forming a metal layer on the region and the substrate; And
    And silicidating the silicon in the region with the metal of the metal layer to form a metal silicide.
    [2" claim-type="Currently amended] The method of claim 1, wherein the silicide blocking layer is formed by depositing silicon oxynitride (SiON) by a PE-CVD method at a temperature of 400 ° C. or less.
    [3" claim-type="Currently amended] The method of claim 2, wherein in the wet etching of the silicide blocking layer, an etchant having an etching selectivity of 10: 1 with respect to oxide is used in the silicon oxynitride.
    [4" claim-type="Currently amended] The method of manufacturing a semiconductor device according to claim 3, wherein a mixed solution of hydrofluoric acid (HF) and water peroxide (H 2 O 2 ) is used as the etchant.
    [5" claim-type="Currently amended] The method of claim 1, wherein the region in which the metal silicide contact is to be formed is a gate region formed on a semiconductor substrate.
    [6" claim-type="Currently amended] The method of claim 1, wherein the region in which the metal silicide contact is to be formed is an active region formed on a surface of the semiconductor substrate.
    [7" claim-type="Currently amended] The method of claim 1, wherein the region in which the metal silicide contact is to be formed is an active region formed on a surface of the semiconductor substrate and a gate region formed on the substrate.
    [8" claim-type="Currently amended] Forming a transistor having a gate electrode and a source / drain region on an active region of the semiconductor substrate;
    Forming a silicide stop layer on the transistor and the substrate by a plasma-enhanced chemical vapor deposition (PE-CVD) method;
    Removing the silicide blocking layer of a portion of the semiconductor substrate by wet etching to form a silicide blocking layer pattern;
    Forming a metal layer on the silicide stop layer pattern, the transistor, and the substrate; And
    And forming a metal silicide by silicidating a silicon in the partial region of the semiconductor substrate on which the silicide blocking layer pattern is not formed with the metal of the metal layer.
    [9" claim-type="Currently amended] The method of claim 8, wherein the silicide blocking layer is formed by depositing silicon oxynitride (SiON) by a PE-CVD method at a temperature of 400 ° C. or less.
    [10" claim-type="Currently amended] The etchant of claim 9, wherein the silicon oxynitride has an etching selectivity of 10: 1 with respect to oxide so as to minimize the consumption of the field oxide layer in the wet etching of the silicide blocking layer. A semiconductor device manufacturing method characterized by the above-mentioned.
    [11" claim-type="Currently amended] The method for manufacturing a semiconductor device according to claim 10, wherein a mixed solution of hydrofluoric acid (HF) and water peroxide (H 2 O 2 ) is used as the etchant.
    [12" claim-type="Currently amended] The method of claim 8, wherein a portion of the semiconductor substrate is a gate region of the transistor.
    [13" claim-type="Currently amended] The method of claim 8, wherein a portion of the semiconductor substrate is a source / drain region of the transistor.
    [14" claim-type="Currently amended] The method of claim 8, wherein the partial region of the semiconductor substrate is a gate region and a source / drain region of the transistor.
    [15" claim-type="Currently amended] The method of claim 8, wherein forming the silicide blocking layer pattern comprises:
    Forming an etching mask on the silicide blocking layer to open a portion of the semiconductor substrate;
    Removing a silicide blocking layer of a portion of the semiconductor substrate by a wet etching method using the etching mask; And
    And removing the etch mask.
    [16" claim-type="Currently amended] The method of claim 15, wherein the etching mask is a photoresist pattern.
    类似技术:
    公开号 | 公开日 | 专利标题
    US8288825B2|2012-10-16|Formation of raised source/drain structures in NFET with embedded SiGe in PFET
    US6326664B1|2001-12-04|Transistor with ultra shallow tip and method of fabrication
    US5757045A|1998-05-26|CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation
    US7338874B2|2008-03-04|Highly integrated semiconductor device with silicide layer that secures contact margin and method of manufacturing the same
    US5723893A|1998-03-03|Method for fabricating double silicide gate electrode structures on CMOS-field effect transistors
    US9035399B2|2015-05-19|Structure for facilitating the simultaneous silicidation of a polysilicon gate and source/drain of a semiconductor device
    US7157358B2|2007-01-02|Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same
    US6790733B1|2004-09-14|Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer
    US6261935B1|2001-07-17|Method of forming contact to polysilicon gate for MOS devices
    KR101027107B1|2011-04-05|Metal gate mosfet by full semiconductor metal alloy conversion
    US5792684A|1998-08-11|Process for fabricating MOS memory devices, with a self-aligned contact structure, and MOS logic devices with salicide, both on a single semiconductor chip
    US6770540B2|2004-08-03|Method of fabricating semiconductor device having L-shaped spacer
    US5994747A|1999-11-30|MOSFETs with recessed self-aligned silicide gradual S/D junction
    US7211515B2|2007-05-01|Methods of forming silicide layers on source/drain regions of MOS transistors
    US5902125A|1999-05-11|Method to form stacked-Si gate pMOSFETs with elevated and extended S/D junction
    KR100218894B1|1999-09-01|Method of manufacturing semiconductor device
    KR100260327B1|2000-07-01|Method of fabricating a raised source/drain mosfet using self-aligned pocl3 for doping gate/source/drain regions
    US7371634B2|2008-05-13|Amorphous carbon contact film for contact hole etch process
    US6599805B2|2003-07-29|Methods of forming transistors and semiconductor processing methods of forming transistor gates
    US6214654B1|2001-04-10|Method for forming super-steep retrograded channel | for CMOS transistor using rapid laser annealing to reduce thermal budget
    KR100498476B1|2005-07-01|MOSFET having recessed channel and fabricating method thereof
    US7176110B2|2007-02-13|Technique for forming transistors having raised drain and source regions with different heights
    US6924180B2|2005-08-02|Method of forming a pocket implant region after formation of composite insulator spacers
    KR100562239B1|2006-03-22|Improved ??? transistor
    KR100736301B1|2007-07-06|A semiconductor integrated circuit device and a method of manufacturing the same
    同族专利:
    公开号 | 公开日
    KR100417894B1|2004-02-11|
    US20020168851A1|2002-11-14|
    US6861369B2|2005-03-01|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-05-10|Application filed by 삼성전자 주식회사
    2001-05-10|Priority to KR20010025552A
    2002-11-18|Publication of KR20020085978A
    2004-02-11|Application granted
    2004-02-11|Publication of KR100417894B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR20010025552A|KR100417894B1|2001-05-10|2001-05-10|Method of forming silicidation blocking layer|
    [返回顶部]